Tesla unveils AI accelerator roadmap: SI6 promises 80x performance

Chips now carry the "SI" name

Tesla has refreshed its AI accelerator roadmap and started branding its chips with "SI" (Super Intelligence) instead of "AI." Accordingly, the existing AI4, AI5 and AI6 chips are now called SI4, SI5 and SI6.

The company expects its sixth-generation inference accelerator, SI6, to deliver 80x the compute performance of the current SI4. SI5 targets 40x the performance of SI4.

Dojo 3 changes architecture

The most notable part of the roadmap is the Dojo D3 training accelerator. Tesla is dropping the wafer-scale integration and distributed SRAM approach used in the first two generations. D3 is based on a multi-chiplet design that combines 2.5D and 3D packaging technologies with stacked HBM memory.

The shift is tied to the memory demands of modern AI models. HBM offers more capacity but brings different trade-offs in latency, bandwidth, packaging and power.

Is wafer-scale integration gone for good?

It is not yet clear whether Tesla has abandoned wafer-scale integration entirely. That approach is expensive and makes the most sense for SRAM-centric architectures. Stacking HBM on top of wafer-scale logic dies adds cooling, manufacturing complexity and cost challenges.

Tesla has not yet shared details such as D3's compute performance or memory capacity.