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AMD EPYC Venice-X: 96 Zen 6 cores and 1152 MB of 3D V-Cache

HardwareNew1 min read

In brief

AMD has announced its EPYC 9006X "Venice-X" server CPUs, arriving in the second half of 2027. The chips pair up to 96 Zen 6 cores with up to 1152 MB of 3D V-Cache and boost clocks reaching 5.3 GHz, targeting HPC and technical compute. Microsoft said the chips will be deployed in its Azure HXv2 instances.

  • Up to 96 Zen 6 cores
  • Up to 1152 MB of 3D V-Cache boosted L3
  • Boost clocks reaching 5.3 GHz
  • Designed for HPC and technical compute
  • Deployment in Azure HXv2 instances
  • Launch in the second half of 2027

A new flagship on the server side

AMD will launch its EPYC 9006X, codenamed "Venice-X", server CPUs in the second half of 2027. The chips combine high-frequency Zen 6 cores with stacked 3D V-Cache memory.

The headline numbers

  • Up to 96 Zen 6 cores
  • Up to 1152 MB of 3D V-Cache boosted L3 cache
  • Boost clocks reaching 5.3 GHz

3D V-Cache means an extra layer of cache stacked on top of the processor. Cache reduces latency in workloads that hit memory frequently.

Who is it for?

According to AMD, Venice-X targets the technical compute and HPC (high-performance computing) segment. The company says the cache-rich design will make the chips a top choice for memory-sensitive workloads.

The cloud side is preparing too

Microsoft has already said the Venice-X chips will be used in Azure's HXv2 instances, a sign that the server chips will find early footing in cloud infrastructure.

Why it matters

In the server CPU market, cache size and core counts translate directly into performance for AI and scientific workloads. AMD's 2027 target signals what the Zen 6 generation will bring to the data center hardware race.

Why it matters

A concrete signal of AMD's 2027 server roadmap for readers following data center and AI infrastructure; the cache and core counts sum up where the competition is heading.

Sources

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